The invention relates in general to electronic circuits and more specifically to differential multiplexers.
Multiplexers allow selection of a signal from a number of signals. In response to a control signal, a multiplexer input receiving the selected signal is connected to the output of the multiplexer. Multiplexers are used in a variety of circuits and environments and are often used in differential signal circuits such as Current Mode Logic (CML) circuits. In a two input multiplexer for example, a differential signal pair is received at a first differential input and another differential signal pair is received at a second differential input. In response to a select signal and its compliment, the signal received at one of the differential signal inputs is directed to a differential output of the multiplexer. Due to their architecture, however, conventional differential multiplexers are limited in that the amplitude or xe2x80x9coutput swingxe2x80x9d of the output signal is often less than a maximum value. Conventional techniques used to increase the amplitude of the output signals result in an increased current draw and power consumption. Therefore, there is a need for a differential multiplexer that efficiently provides an output signal with a maximum amplitude.
In an exemplary embodiment of the invention, the amplitude of a differential output signal at a differential multiplexer is efficiently maximized by presenting, in response to a differential selection signal, a high impedance to each output port of each differential transistor of a non-selected differential transistor pair. The exemplary differential multiplexer includes a selection transistor connected to the output port of each transistor of a differential transistor pair that receives a differential input signal. In response to the differential selection signal, each of the selection transistors connected to the non-selected differential transistor pair is placed in an off state resulting in a high impedance between the output ports of the transistors of the non-selected differential transistor pair.